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Inter-integrated circuit (I 2 C) interface
Bit 8 ITERREN : Error interrupt enable
0: Error interrupt disabled
1: Error interrupt enabled
This interrupt is generated when:
–BERR = 1
–ARLO = 1
–AF = 1
–OVR = 1
–PECERR = 1
–TIMEOUT = 1
–SMBAlert = 1
Bits 7:6 Reserved, forced by hardware to 0.
Bits 5:0 FREQ[5:0] : Peripheral clock frequency
Input clock frequency must be programmed to generate correct timings
The allowed range is between 2 MHz and 36 MHz
000000: Not allowed
000001: Not allowed
000010: 2 MHz
...
100100: 36 MHz
Higher than 100100: Not allowed
RM0008
24.6.3
Own address register 1 (I2C_OAR1)
Reset Address offset: 0x08
Value: 0x0000
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ADD
MODE
Res.
Reserved
ADD[9:8]
ADD[7:1]
ADD0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bit 15 ADDMODE Addressing mode (slave mode)
0: 7-bit slave address (10-bit address not acknowledged)
1: 10-bit slave address (7-bit address not acknowledged)
Bit 14 Must be configured and kept at 1.
Bits 13:10 Reserved, forced by hardware to 0.
Bits 9:8 ADD[9:8] : Interface address
7-bit addressing mode: don’t care
10-bit addressing mode: bits9:8 of address
Bits 7:1 ADD[7:1] : Interface address
bits 7:1 of address
Bit 0 ADD0 : Interface address
7-bit addressing mode: don’t care
10-bit addressing mode: bit 0 of address
644/995
Doc ID 13902 Rev 9
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